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Dr Shounak Chakraborty's Outputs (16)

HotReRAM: A Performance-Power-Thermal Simulation Framework for ReRAM based Caches (2025)
Journal Article
Chakraborty, S., Bunnam, T., Arunruerk, J., Agarwal, S., Yu, S., Shafik, R., & Sjalander, M. (online). HotReRAM: A Performance-Power-Thermal Simulation Framework for ReRAM based Caches. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, https://doi.org/10.1109/TCAD.2025.3546855

This paper proposes a comprehensive thermal modeling and simulation framework, HotReRAM, for resistive RAM (ReRAM)-based caches that is verified against a memristor circuit-level model. The simulation is driven by power traces based on cache accesses... Read More about HotReRAM: A Performance-Power-Thermal Simulation Framework for ReRAM based Caches.

MAFin: Maximizing Accuracy in FinFET based Approximated Real-Time Computing (2024)
Presentation / Conference Contribution
Chakraborty, S., Saha, S., Sjalander, M., & Mcdonald-Maier, K. (2024, June). MAFin: Maximizing Accuracy in FinFET based Approximated Real-Time Computing. Presented at DAC '24: 61st ACM/IEEE Design Automation Conference, San Francisco CA USA

We propose MAFin that exploits the unique temperature effect inversion (TEI) property of a FinFET based multicore platform, where processing speed increases with temperature, in the context of approximate real-time computing. In approximate real-time... Read More about MAFin: Maximizing Accuracy in FinFET based Approximated Real-Time Computing.

ARCTIC: Approximate Real-Time Computing in a Cache-Conscious Multicore Environment (2024)
Journal Article
Saha, S., Chakraborty, S., Agarwal, S., Själander, M., & McDonald-Maier, K. D. (2024). ARCTIC: Approximate Real-Time Computing in a Cache-Conscious Multicore Environment. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 43(10), 2944-2957. https://doi.org/10.1109/tcad.2024.3384442

Improving result-accuracy in approximate computing (AC)-based time-critical systems, without violating power constraints of the underlying circuitry, is gradually becoming challenging with the rapid progress in technology scaling. The execution span... Read More about ARCTIC: Approximate Real-Time Computing in a Cache-Conscious Multicore Environment.

TREAFET: Temperature-Aware Real-Time Task Scheduling for FinFET based Multicores (2024)
Journal Article
Chakraborty, S., Sharma, Y., & Moulik, S. (2024). TREAFET: Temperature-Aware Real-Time Task Scheduling for FinFET based Multicores. ACM Transactions on Embedded Computing Systems, 23(4), Article 61. https://doi.org/10.1145/3665276

The recent shift in the VLSI industry from conventional MOSFET to FinFET for designing contemporary chip-multiprocessor (CMP) has noticeably improved hardware platforms’ computing capabilities, but at the cost of several thermal issues. Unlike the co... Read More about TREAFET: Temperature-Aware Real-Time Task Scheduling for FinFET based Multicores.

NTHPC: Embracing Near-Threshold Operation for High Performance Multi-core Systems (2023)
Presentation / Conference Contribution
Chakraborty, S., Safarpour, M., & Silvén, O. (2023, July). NTHPC: Embracing Near-Threshold Operation for High Performance Multi-core Systems. Presented at SAMOS 2023, Samos, Greece

System-on-Chip (SoC) manufacturers use Core Level Redundancy (CLR) scheme to cope with fabrication defects. By providing redundancy with extra cores and logic blocks, CLR ensures delivering performance even if a small number of the functional units a... Read More about NTHPC: Embracing Near-Threshold Operation for High Performance Multi-core Systems.

Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR) (2023)
Presentation / Conference Contribution
Agarwal, S., Chakraborty, S., & Själander, M. (2023, July). Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR). Presented at 2023 60th ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA

The increasing use of chiplets, and the demand for high-performance yet low-power systems, will result in heterogeneous systems that combine both CPUs and accelerators (e.g., general-purpose GPUs). Chiplet based designs also enable the inclusion of e... Read More about Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR).

ACCURATE: Accuracy Maximization for Real-Time Multicore Systems With Energy-Efficient Way-Sharing Caches (2022)
Journal Article
Saha, S., Chakraborty, S., Zhai, X., Ehsan, S., & McDonald-Maier, K. D. (2022). ACCURATE: Accuracy Maximization for Real-Time Multicore Systems With Energy-Efficient Way-Sharing Caches. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 41(12), 5246-5260. https://doi.org/10.1109/tcad.2022.3161407

Improving result accuracy in approximate computing (AC)-based real-time applications without violating deadlines has recently become an active research domain. Execution time of AC real-time tasks can individually be separated into: execution of the... Read More about ACCURATE: Accuracy Maximization for Real-Time Multicore Systems With Energy-Efficient Way-Sharing Caches.

DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious Multicore (2022)
Journal Article
Saha, S., Chakraborty, S., Agarwal, S., Gangopadhyay, R., Sjalander, M., & McDonald-Maier, K. (2023). DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious Multicore. IEEE Transactions on Parallel and Distributed Systems, 34(2), 718-733. https://doi.org/10.1109/tpds.2022.3228751

Enhancing result-accuracy in approximate computing (AC) based real-time systems, without violating power constraints of the underlying hardware, is a challenging problem. Execution of such AC real-time applications can be split into two parts: (i) th... Read More about DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious Multicore.

STIFF: thermally safe temperature effect inversion aware FinFET based multi-core (2022)
Presentation / Conference Contribution
Chakraborty, S., Soteriou, V., & Själander, M. (2022, May). STIFF: thermally safe temperature effect inversion aware FinFET based multi-core. Presented at CF '22: 19th ACM International Conference on Computing Frontiers, Turin Italy

FinFET, a non-planar device, has become the prevalent choice for chip-multiprocessor (CMP) designs due to its lower leakage and improved scalability as compared to planar CMOS devices. FinFETs are fundamentally different from conventional CMOS circui... Read More about STIFF: thermally safe temperature effect inversion aware FinFET based multi-core.

RESTORE: Real-Time Task Scheduling on a Temperature Aware FinFET based Multicore (2022)
Presentation / Conference Contribution
Sharma, Y., Moulik, S., & Chakraborty, S. (2022, March). RESTORE: Real-Time Task Scheduling on a Temperature Aware FinFET based Multicore. Presented at 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium

In this work, we propose RESTORE that exploits the unique thermal feature of FinFET based multicore platforms, where processing speed increases with temperature, in the context of time-criticality to meet other design constraints of real-time systems... Read More about RESTORE: Real-Time Task Scheduling on a Temperature Aware FinFET based Multicore.

Prepare: Power-Aware Approximate Real-time Task Scheduling for Energy-Adaptive QoS Maximization. (2021)
Journal Article
Chakraborty, S., Saha, S., Själander, M., & Mcdonald-Maier, K. (2021). Prepare: Power-Aware Approximate Real-time Task Scheduling for Energy-Adaptive QoS Maximization. ACM Transactions on Embedded Computing Systems, 20(5s), 1-25. https://doi.org/10.1145/3476993

Achieving high result-accuracy in approximate computing (AC) based real-time applications without violating power constraints of the underlying hardware is a challenging problem. Execution of such AC real-time tasks can be divided into the execution... Read More about Prepare: Power-Aware Approximate Real-time Task Scheduling for Energy-Adaptive QoS Maximization..

WaFFLe: Gated Cache-Ways with Per-Core Fine-Grained DVFS for Reduced On-Chip Temperature and Leakage Consumption (2021)
Journal Article
Chakraborty, S., & Själander, M. (2021). WaFFLe: Gated Cache-Ways with Per-Core Fine-Grained DVFS for Reduced On-Chip Temperature and Leakage Consumption. ACM Transactions on Architecture and Code Optimization, 18(4), 1-25. https://doi.org/10.1145/3471908

Managing thermal imbalance in contemporary chip multi-processors (CMPs) is crucial in assuring functional correctness of modern mobile as well as server systems. Localized regions with high activity, e.g., register files, ALUs, FPUs, and so on, exper... Read More about WaFFLe: Gated Cache-Ways with Per-Core Fine-Grained DVFS for Reduced On-Chip Temperature and Leakage Consumption.

ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache (2021)
Presentation / Conference Contribution
Agarwal, S., & Chakraborty, S. (2021, July). ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache. Presented at 2021 IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors (ASAP), NJ, USA

Exhibition of potential advantages of high density, non-volatility, and low static power consumption makes STTRAM a credible successor to SRAM in caches. However, higher write energy and latency of the STT-RAM limit its potential towards commercial u... Read More about ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache.

SEAMERS: A Semi-partitioned Energy-Aware scheduler for heterogeneous MulticorE Real-time Systems (2020)
Journal Article
Moulik, S., Das, Z., Devaraj, R., & Chakraborty, S. (2021). SEAMERS: A Semi-partitioned Energy-Aware scheduler for heterogeneous MulticorE Real-time Systems. The Journal of Systems Architecture: Embedded Software Design, 114, Article 101953. https://doi.org/10.1016/j.sysarc.2020.101953

Over the years, the nature of processing platforms is witnessing a significant shift in most of the battery supported real-time systems, which now support a combination of specialized multicores to meet the demands of modern applications. Devising en... Read More about SEAMERS: A Semi-partitioned Energy-Aware scheduler for heterogeneous MulticorE Real-time Systems.