All Outputs (5)

PTSC: probability, time and shared-variable concurrency (2009)
Journal Article
Zhu, H., Qin, S., He, J., & Bowen, J. (2009). PTSC: probability, time and shared-variable concurrency. Innovations in Systems and Software Engineering, 5(4), 271-284. https://doi.org/10.1007/s11334-009-0100-9

Complex software systems typically involve features like time, concurrency and probability, where probabilistic computations play an increasing role. It is challenging to formalize languages comprising all these features. In this paper, we integrate... Read More about PTSC: probability, time and shared-variable concurrency.

Verifying BPEL-like Programs with Hoare Logic (2008)
Journal Article
Luo, C., Qin, S., & Qiu, Z. (2008). Verifying BPEL-like Programs with Hoare Logic. Frontiers of Computer Science in ChinabOnline, 2(4), 344-356. https://doi.org/10.1007/s11704-008-0039-2

The WS-BPEL language has recently become a de facto standard for modeling Web-based business processes. One of its essential features is the fully programmable compensation mechanism. To understand it better, many recent works have mainly focused on... Read More about Verifying BPEL-like Programs with Hoare Logic.

Timed Automata Patterns (2008)
Journal Article
Dong, J., Hao, P., Qin, S., Sun, J., & Wang, Y. (2008). Timed Automata Patterns. IEEE Transactions on Software Engineering, 34(6), 844-859. https://doi.org/10.1109/tse.2008.52

Timed Automata have proven to be useful for specification and verification of real-time systems. System design using Timed Automata relies on explicit manipulation of clock variables. A number of automated analyzers for Timed Automata have been devel... Read More about Timed Automata Patterns.

From statecharts to verilog : a formal approach to hardware/software co-specification (2006)
Journal Article
Qin, S., Chin, W., He, J., & Qiu, Z. (2006). From statecharts to verilog : a formal approach to hardware/software co-specification. Innovations in Systems and Software Engineering, 2(1), 17-38. https://doi.org/10.1007/s11334-005-0020-2

Hardware-Software co-specification is a critical phase in co-design. Our co-specification process starts with a high level graphical description in Statecharts and ends with an equivalent parallel composition of hardware and software descriptions in... Read More about From statecharts to verilog : a formal approach to hardware/software co-specification.

An Algebraic Hardware/Software Partitioning Algorithm (2002)
Journal Article
Qin, S., He, J., Qiu, Z., & Zhang, N. (2002). An Algebraic Hardware/Software Partitioning Algorithm. Journal of Computer Science and Technology, 17(3), 284-294

Hardware and software co-design is a design technique which delivers computer systems comprising hardware and software components. A critical phase of the co-design process is to decompose a program into hardware and software. This paper proposes an... Read More about An Algebraic Hardware/Software Partitioning Algorithm.