All Outputs (7)

MAFin: Maximizing Accuracy in FinFET based Approximated Real-Time Computing (2024)
Presentation / Conference Contribution
Chakraborty, S., Saha, S., Sjalander, M., & Mcdonald-Maier, K. (2024, June). MAFin: Maximizing Accuracy in FinFET based Approximated Real-Time Computing. Presented at DAC '24: 61st ACM/IEEE Design Automation Conference, San Francisco CA USA

We propose MAFin that exploits the unique temperature effect inversion (TEI) property of a FinFET based multicore platform, where processing speed increases with temperature, in the context of approximate real-time computing. In approximate real-time... Read More about MAFin: Maximizing Accuracy in FinFET based Approximated Real-Time Computing.

TEEMO: Temperature Aware Energy Efficient Multi-Retention STT-RAM Cache Architecture (2024)
Presentation / Conference Contribution
Agarwal, S., Chakraborty, S., & Själander, M. (2024, May). TEEMO: Temperature Aware Energy Efficient Multi-Retention STT-RAM Cache Architecture. Presented at 2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS), San Francisco, CA, USA

NTHPC: Embracing Near-Threshold Operation for High Performance Multi-core Systems (2023)
Presentation / Conference Contribution
Chakraborty, S., Safarpour, M., & Silvén, O. (2023, July). NTHPC: Embracing Near-Threshold Operation for High Performance Multi-core Systems. Presented at SAMOS 2023, Samos, Greece

System-on-Chip (SoC) manufacturers use Core Level Redundancy (CLR) scheme to cope with fabrication defects. By providing redundancy with extra cores and logic blocks, CLR ensures delivering performance even if a small number of the functional units a... Read More about NTHPC: Embracing Near-Threshold Operation for High Performance Multi-core Systems.

Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR) (2023)
Presentation / Conference Contribution
Agarwal, S., Chakraborty, S., & Själander, M. (2023, July). Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR). Presented at 2023 60th ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA

The increasing use of chiplets, and the demand for high-performance yet low-power systems, will result in heterogeneous systems that combine both CPUs and accelerators (e.g., general-purpose GPUs). Chiplet based designs also enable the inclusion of e... Read More about Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR).

STIFF: thermally safe temperature effect inversion aware FinFET based multi-core (2022)
Presentation / Conference Contribution
Chakraborty, S., Soteriou, V., & Själander, M. (2022, May). STIFF: thermally safe temperature effect inversion aware FinFET based multi-core. Presented at CF '22: 19th ACM International Conference on Computing Frontiers, Turin Italy

FinFET, a non-planar device, has become the prevalent choice for chip-multiprocessor (CMP) designs due to its lower leakage and improved scalability as compared to planar CMOS devices. FinFETs are fundamentally different from conventional CMOS circui... Read More about STIFF: thermally safe temperature effect inversion aware FinFET based multi-core.

RESTORE: Real-Time Task Scheduling on a Temperature Aware FinFET based Multicore (2022)
Presentation / Conference Contribution
Sharma, Y., Moulik, S., & Chakraborty, S. (2022, March). RESTORE: Real-Time Task Scheduling on a Temperature Aware FinFET based Multicore. Presented at 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium

In this work, we propose RESTORE that exploits the unique thermal feature of FinFET based multicore platforms, where processing speed increases with temperature, in the context of time-criticality to meet other design constraints of real-time systems... Read More about RESTORE: Real-Time Task Scheduling on a Temperature Aware FinFET based Multicore.

ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache (2021)
Presentation / Conference Contribution
Agarwal, S., & Chakraborty, S. (2021, July). ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache. Presented at 2021 IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors (ASAP), NJ, USA

Exhibition of potential advantages of high density, non-volatility, and low static power consumption makes STTRAM a credible successor to SRAM in caches. However, higher write energy and latency of the STT-RAM limit its potential towards commercial u... Read More about ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache.